General Purpose Registers - Register Types

Encoding of the General Purpose Registers
The encoding for the general purpose registers is shown in the table; it will be used in place of ra, rb and rc in the instruction formats shown above. Note that this is a simple 5 bit encoding. ra, rb and rc are names of  fields used as “place-holders”, and can represent any one of these 32 registers. An exception is rb = 0; it does not mean the register R0, rather it means no operand. This will be explained in the following discussion.

Type A
Type A is used for only two instructions:
  •  No operation or nop, for which the op-code = 0. This is useful in pipelining
  • Stop operation stop, the op-code is 31 for this instruction.
Both of these instructions do not need an operand (are 0-operand instructions).
 Type B
Type B format includes three instructions; all three use relative addressing mode. These are
  •  The ldr instruction, used to load register from memory using a relative address.
(op-code = 2).
o Example:
ldr R3, 56
This instruction will load the register R3 with the contents of the memory
location M [PC+56]
  • The lar instruction, for loading a register with relative address (op-code = 6)
    o Example:
    lar R3, 56
    This instruction will load the register R3 with the relative address itself
    (PC+56).
  •  The str is used to store register to memory using relative address (op-code = 4)
    o Example:
    str R8, 34
    This instruction will store the register R8 contents to the memory location
    M [PC+34]
The effective address is computed at run-time by adding a constant to the PC. This makes
the instructions re-locatable.

Type C
Type C format has three load/store instructions, plus three ALU instructions. These load/ store instructions are
  •  ld, the load register from memory instruction (op-code = 1)
o Example 1:
ld R3, 56
This instruction will load the register R3 with the contents of the memory
location M [56]; the rb field is 0 in this instruction, i.e., it is not used. This
is an example of direct addressing mode.
o Example 2:
ld R3, 56(R5)
The contents of the memory location M [56+R [5]] are loaded to the
register R3; the rb field ≠ 0. This is an instance of indexed addressing
mode.

  • la is the instruction to load a register with an immediate data value (which can be an address) (op-code = 5 )
o Example1:
la R3, 56
The register R3 is loaded with the immediate value 56. This is an instance
of immediate addressing mode.
o Example 2:
la R3, 56(R5)
The register R3 is loaded with the indexed address 56+R [5]. This is an
example of indexed addressing mode.
  • The st instruction is used to store register contents to memory (op-code = 3)
o Example 1:
st R8, 34
This is the direct addressing mode; the contents of register R8 (R [8]) are
stored to the memory location M [34]
o Example 2:
st R8, 34(R6)
An instance of indexed addressing mode, M [34+R [6]] stores the contents
of R8(R [8])
The ALU instructions are

  • addi, immediate 2‟s complement addition (op-code = 13)
o Example:
addi R3, R4, 56
R[3] R[4]+56 (rb field = R4)
  •  andi, the instruction to obtain immediate logical AND, (op-code = 42 )
o Example:
andi R3, R4, 56
R3 is loaded with the immediate logical AND of the contents of register
R4 and 56(constant value)
  •  ori, the instruction to obtain immediate logical OR (op-code = 23 )
o Example:
ori R3, R4, 56
R3 is loaded with the immediate logical OR of the contents of register R4
and 56(constant value)
Note:
  1.  Since the constant c2 field is 17 bits,
    • For direct addressing mode, only the first 216 bytes of memory can be accessed (or the last 216 bytes if c2 is negative)
    •  In case of the la instruction, only constants with magnitudes less than ±216 can be loaded
    •  During address calculation using c2, sign extension to 32 bits must be performed before the addition
  2.  Type C instructions, with some modifications, may also be used for
    shift instructions. Note the modification in the following figure.
     
The four shift instructions are
  • shr is the instruction used to shift the bits right by using value in (5-bit) c3 field(shift count)
  • (op-code = 26)
    Example:
    shr R3, R4, 7
    shift R4 right 7 times in to R3. Immediate addressing mode is used.
  • shra, arithmetic shift right by using value in c3 field (op-code = 27)
    Example:
    shra R3, R4, 7
    This instruction has the effect of shift R4 right 7 times in to R3. Immediate
    addressing mode is used.
  • The shl instruction is for shift left by using value in (5-bit) c3 field (op-code = 28)
    Example:
    shl R8, R5, 6
    shift R5 left 6 times in to R8. Immediate addressing mode is used.
  • shc, shift left circular by using value in c3 field (op-code = 29)
    Example:
    shc R3, R4, 3
    shift R4 circular 3 times in to R3. Immediate addressing mode is used.

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